Various power supply configurations are known in the art. Some power supply designs are based on Low Drop-Out (LDO) voltage regulators. For example, U.S. Pat. No. 5,672,959, whose disclosure is incorporated herein by reference, describes a low drop-out regulator circuit having first and second feedback loops. A first local feedback loop is a high-speed, high-bandwidth loop that actively rejects noise from the input source to the regulator. A second feedback loop, having lower speed and a correspondingly lower bandwidth than the first feedback loop, regulates the output voltage.
U.S. Patent Application Publication 2005/0189931, whose disclosure is incorporated herein by reference, describes a power supply unit comprising a series regulator and a switching DC-DC converter controlled by a PWM signal and connected in parallel with the series regulator, which are switchable, enabled by a mode instruction signal depending on the magnitude of a load current.
U.S. Patent Application Publication 2007/0152742, whose disclosure is incorporated herein by reference, describes a low dropout voltage regulator comprising a supply input terminal for connecting a supply voltage and an output terminal for providing a regulated output voltage, a reference voltage source, and an output voltage monitor. An error amplifier has an output supplying an error signal in response to deviations of the regulated output voltage from a desired target output voltage value at the output terminal. A power output FET has a drain-source channel connected between the supply input terminal and the output terminal of the voltage regulator. A gate terminal of the power output FET is controlled by the error amplifier via a driver FET such that deviations of the regulated output voltage are minimized.
U.S. Patent Application Publication 2008/0224680, whose disclosure is incorporated herein by reference, describes a voltage regulator. To enhance the safety of the voltage regulator, a control circuit controls a PMOS to be turned on and operates so as to increase the output voltage when the output voltage drops transiently due to rapid fluctuations of a load connected to an output terminal and predetermined conditions are not satisfied, and does not perform an operation for increasing the output voltage and causes the protection circuit to protect the voltage regulator when the output voltage drops transiently and the predetermined conditions are satisfied.
U.S. Patent Application Publication 2010/0277148, whose disclosure is incorporated herein by reference, describes a voltage regulator having one or more discharger circuits that compensate for low on-chip output capacitance and a slow loop response time. In one embodiment, the voltage regulator includes an output transistor coupled to an output voltage line, an output voltage sensing arrangement coupled to the output voltage line for producing an output feedback voltage, and an error amplifier coupled to the output feedback voltage, the output transistor, and a reference voltage for applying feedback control to the output transistor. A first discharger circuit is coupled to the output voltage line and to a reference potential, the first discharger circuit being triggered by a steep-rise overvoltage condition. In another embodiment, a combination of fast and slow discharger circuits is used to improve the load step response.
U.S. Patent Application Publication 2014/0239929, whose disclosure is incorporated herein by reference, describes a low dropout regulator comprising an output transistor with a controlled section coupled between a first supply terminal and an output terminal, and a differential amplifier that comprises a feedback input coupled to the output terminal, a reference input for receiving a reference voltage, an output connected to a control terminal of the output transistor, and at least one pair of input transistors. The input transistors of each pair are commonly connected to a tail current source of the respective pair. A control terminal of a respective first transistor of each pair is connected to the reference input. A control terminal of a respective second transistor of each pair is connected to the feedback input. A first capacitive element is coupled between the output terminal and the common connection of the input transistors of one pair with their respective tail current source. A second capacitive element is coupled between a second supply terminal and the common connection of the input transistors of one pair with their respective tail current source.
U.S. Pat. No. 7,498,780, whose disclosure is incorporated herein by reference, describes a linear voltage regulating circuit with undershoot minimization. The circuit includes a voltage regulator, a converting circuit, a capacitive device, a first current mirror module, and a second current mirror module. The voltage regulator has a first output producing the regulated output voltage and a second output producing a pass voltage. The converting circuit converts the pass voltage into a first current and a second current passing through a first converting node and a second converting node respectively, where the first current charges/discharges the capacitive device. The first current mirror module has a first current mirror path coupled to the first converting node and a second current mirror path coupled to the second converting node. The second current mirror module has a first current mirror path coupled to the second converting node and a second current mirror path coupled to the first output.